1. Field of the Invention
The present invention relates to an impedance adjusting circuit.
2. Description of Related Art
FIG. 3 is a pattern diagram of an output buffer included in a semiconductor integrated circuit and a transmission line connected thereto. The output buffer includes an output impedance of Za. The transmission line includes a characteristic impedance of Zb. If the output impedance Za does not match the impedance Zb of the transmission line, an output signal from the output buffer is reflected. Then, a reflected wave generated by the reflection and an interference with the output signal cause to deteriorate the quality of a signal to be transmitted. Therefore, it is necessary to match the output buffer Za of the semiconductor integrated circuit and the impedance Zb of the transmission line.
However, the characteristic impedance Zb of the transmission line is usually fixed. Thus, it is necessary to adjust the output impedance Za of the output buffer to a value close to Zb. FIG. 4 illustrates the configuration of an output impedance adjusting circuit 1 according to a related art. As illustrated in FIG. 4, the output impedance adjusting circuit 1 includes replica buffer circuits 11 and 21, control circuits 12 and 22, comparators CMP1 and CMP2, and external terminals P1 and P2.
The replica buffer circuit 11 includes multiple NMOS transistors. These multiple NMOS transistors are connected in parallel between the external terminal P1 and a ground voltage terminal VSS. The configuration of this replica buffer circuit 11 is the same as that of the pull-down side circuit of the output buffer. That is, the replica buffer circuit 11 includes the same output impedance as the pull-down side circuit (hereinafter referred to as a pull-down buffer circuit) of the output buffer.
The replica buffer circuit 21 includes multiple PMOS transistors. These PMOS transistors are connected in parallel between a power supply voltage terminal VDD and the external terminal P2. The configuration of this replica buffer circuit 21 is the same as that of the pull-up side circuit of the output buffer. That is, the replica buffer circuit 21 includes the same output impedance as the pull-up side circuit (hereinafter referred to as a pull-up buffer circuit) of the output buffer.
The comparator CMP1 compares an output voltage level Vp1, which is output from the replica buffer circuit 11 to the external output terminal P1, with a reference voltage Vref. The comparator CMP2 compares an output voltage level Vp2, which is output from the replica buffer circuit 21 to the external output terminal P2, with the reference voltage Vref.
The control circuit 12 includes a counter, for example, and increases the counter according to the comparison result of the comparator CMP1. Then, the control circuit 12 outputs a control signal CN according to the count value. The control circuit 12 controls so that the NMOS transistors included in the replica buffer circuit 11 are turned on sequentially by the control signal CN. In a similar way, the control circuit 22 also includes a counter and increases the counter according to the comparison result of the comparator CMP2. Then, the control circuit 22 outputs a control signal CP according to the count value. The control circuit 22 controls so that the PMOS transistors included in the replica buffer circuit 21 are turned on sequentially by the control signal CP.
The external terminals P1 and P2 are respectively connected to replica resistors RrepU and RrepD which have the same impedance as the characteristic impedance of the transmission line in which the output buffer is connected thereto. Note that the replica resistor RrepU is connected to the power supply voltage terminal VDD. The replica resistor RrepD is connected to the ground voltage terminal VSS.
An operation example of the output impedance adjusting circuit 1 illustrated in FIG. 4 is explained hereinafter briefly. Note that the reference voltage Vref shall be ½ VDD. Further, at an initial state, all of the NMOS transistors and the PMOS transistors included in the replica buffer circuits 11 and 21 are in an OFF state.
Firstly, the comparator CMP1 compares the voltage Vp1 of the external output terminal P1 with the reference voltage Vref. If the voltage Vp1 is higher than the reference voltage Vref, the comparison result is transmitted to the control circuit 12. The control circuit 12 increases the counter according to the comparison result, and sequentially turns on the NMOS transistors. Then, if the voltage Vp1 is reduced to be the same level as the reference voltage Vref, the control circuit 12 stops turning on the NMOS transistors according to the comparison result of the comparator CMP1. The impedance of the replica buffer circuit 11, which corresponds to the number of NMOS transistors that are in an ON state at this time, becomes the same resistance value of the replica resistor RrepU.
Similarly, the comparator CMP2 compares the voltage Vp2 of the external output terminal P2 with the reference voltage Vref. If the voltage Vp2 is lower than the reference voltage Vref, the comparison result is transmitted to the control circuit 22. The control circuit 22 increases the counter according to the comparison result, and sequentially turns on the PMOS transistors. Then, if the voltage Vp2 increases to be the same level as the reference voltage Vref, the control circuit 22 stops turning on the PMOS transistors according to the comparison result of the comparator CMP2. The impedance of the replica buffer circuit 21, which corresponds to the number of PMOS transistors that are in an ON state at this time, becomes the same resistance value of the replica resistor RrepD.
As described above, the output buffer (not illustrated) includes a pull-down buffer circuit and a pull-up buffer circuit that have the same configuration as the replica buffer circuits 11 and 12. The output impedance adjusting circuit 1 transmits the control signals CN and CP held by the control circuits 12 and 22 respectively to the pull-down buffer circuit and the pull-up buffer circuit. Accordingly, the output buffer can generate an output impedance corresponding to these control signals CN and CP. As a result, the output impedance of the output buffer can be matched with characteristic impedance of the transmission line.
However, two terminals are required for adjusting the impedance for pull-down and pull-up in the abovementioned output impedance adjusting circuit 1. In recent years, there is an increasing demand for reducing the external terminals by the miniaturization of a package of a semiconductor integrated circuit. Therefore, the technique with reduced number of terminals for impedance adjustment is disclosed in Japanese Unexamined Patent Application Publication No. 2000-59202. FIG. 5 illustrates the circuit configuration of an output impedance adjusting circuit 2 disclosed in Japanese Unexamined Patent Application Publication No. 2000-59202 as a prior art.
As illustrated in FIG. 5, the output impedance adjusting circuit 2 includes replica buffer circuits 11, 21a, and 21b, control circuits 12 and 22, comparators CMP1 and CMP2, and an external terminal P2. Note that in FIG. 5, the components with the same codes as in FIG. 4 indicate the same or similar components as those therein. Further note that the replica buffer circuits 21a and 21b have the same configuration as the replica buffer circuit 21 of FIG. 4. However, the replica buffer circuit 21a is connected between the power supply voltage terminal VDD and the external terminal P2. The replica buffer circuit 21b is connected between the power supply voltage terminal VDD and the node A. Moreover, the control circuit 22 outputs the control signal CP to both of the replica buffer circuits 21a and 21b. On the other hand, the replica buffer circuit 11 is connected between the node A and the ground voltage terminal VSS. Then, the comparator CMP1 compares the reference voltage Vref with the voltage level of the node A.
An operation example of the output impedance adjusting circuit 2 illustrated in FIG. 5 is explained hereinafter briefly. Note that the reference voltage Vref shall be ½ VDD. At an initial state, all of the NMOS transistors and PMOS transistors included in the replica buffer circuits 11, 21a, and 21b are in an OFF state.
Firstly, in a similar way as the output impedance adjusting circuit 1, by the operation of the comparator CMP2 and the control circuit 22, the impedance of the replica buffer circuit 21a becomes the same resistance value as the replica resistor RrepD, which is connected to the external terminal P2. As the control signal CP of the control circuit 22 is output also to the replica buffer circuit 21b, the voltage level of the node A changes. The comparator CMP1 and the control circuit 12 uses the control signal CN to control the replica buffer circuit 11 so that the potentials of the node A and the reference voltage Vref are matched.
Then, the control signals CN and CP, as at when the potentials of the external terminal P2 and the node A are stabilized, are transmitted to the output buffer (not illustrated) from the output impedance adjusting circuit 2, and thereby enabling the output buffer to generate an output impedance that corresponds to the control signals CN and CP.